Type-safe Interfaces for Heterogeneous Embedded Systems.

One YAML. Four Languages. Generated code for FPGA, C, C++ and Python — including glue code across all boundaries.

Getting Started View Example

embgen doesn't replace your code generator — it's the missing layer that keeps your hardware and software interfaces consistent.

The Problem

Manual Interface Synchronization

FPGA engineer changes a register — firmware developer and test team must manually follow suit. Every change is a risk.

Error-prone Glue Layers

FPGA-to-C, C-to-C++, C++-to-Python transitions are hand-written. Type mismatches and alignment errors cost days of debugging.

No Single Source of Truth

Register docs in Excel, C headers maintained manually, Python wrappers outdated. Three truths — none of them current.

Features

One YAML file. Four languages. Fully type-safe.

Code Generation

Generate type-safe code for VHDL, C, C++ and Python from a single YAML definition. Consistent and reproducible.

  • VHDL: AXI-Lite Entities, Config Packages, AXI-Stream FIFO
  • C: volatile structs, bitfield macros, HAL functions, DMA ring buffer
  • C++: RAII wrappers, virtual interfaces, std::function observer, template ring buffer
  • Python: ctypes descriptors, cffi/pybind11, dataclasses
embgen generate system.yml --targets vhdl,c,cpp,python

Automatic Glue Code

Every language boundary is automatically bridged — type-safe and without boilerplate.

  • FPGA → C: Platform HAL (Linux/bare-metal), mmap, DMA, IRQ handler
  • C → C++: extern "C" wrapper, RAII bridge, std::function event bridge
  • C++ → Python: pybind11 modules or ctypes fallback
  • CMakeLists.txt + pyproject.toml with --build-system flag
embgen generate system.yml --build-system

Incremental Generation

Content hash comparison instead of timestamps — only changed files are written.

  • SHA256-based content hash excluding timestamp lines
  • --force flag: rewrite everything, --clean: remove orphans
  • Manifest-based cleanup: removed interfaces = removed files
  • Status: "65 file(s) (3 written, 62 unchanged)"
embgen generate system.yml --clean

Compliance & Traceability

CycloneDX SBOM, compliance reports and seamless embtrace integration for EU CRA.

  • CycloneDX 1.5 SBOM export from interfaces.yaml
  • Interface compliance reports: orphans, SHA256 integrity, coverage
  • interfaces.yaml as integration artifact for embtrace
  • PlantUML diagrams and manifest diff
embgen sbom interfaces.yaml --format json

5 Interface Types

Each type generates language-specific artifacts — from VHDL entities to Python descriptors.

register

Memory-mapped read/write registers with bitfield definitions and automatic address calculation.

VHDL: AXI-Lite Slave Entity
C: volatile struct + bitfield macros
C++: RAII register wrapper
Python: ctypes descriptors

function

Synchronous call/return. For HAL abstractions and driver APIs.

C: HAL function prototypes + error codes
C++: Pure virtual interface
Python: ctypes/cffi wrapper

event

Asynchronous notifications. IRQs, callbacks and observer pattern.

VHDL: IRQ Pulse
C: IRQ Handler
C++: std::function Observer
Python: queue/signal

stream

Continuous data streams. For high-throughput sensor data and signal processing.

VHDL: AXI-Stream Entity (FIFO)
C: DMA Ring Buffer
C++: span/iterator Template
Python: shared memory

config

Static parameters. Compile-time constants consistent across all languages.

VHDL: Generics (Package)
C: const struct
C++: constexpr
Python: dataclass

4x4 Boundary Matrix

Every provider/consumer combination generates matching glue code. Automatically resolved.

fpga → c: mmap + DMA + IRQ
c → cpp: extern "C" + RAII
cpp → python: pybind11 / ctypes
internal: Language-native calls

Import / Export

Import existing models, export to industry standards.

Enterprise Architect / XMI

Import

Convert XMI 2.1 exports from Enterprise Architect directly into an embgen system.yml. Stereotype-based mapping.

embgen import xmi diagram.xmi --output system.yml

SystemRDL

Import

Import SystemRDL register definitions (.rdl) directly. Access mapping, reset values, field descriptions.

embgen import systemrdl registers.rdl -o system.yml

IP-XACT (IEEE 1685)

Import Export

Import and export IP-XACT XML. Dual namespace support (2014 + 2009) for FPGA vendor tools.

embgen import ip-xact component.xml -o system.yml
embgen export ip-xact system.yml -o component.xml

SysML v2

Import

Import SysML v2 JSON or REST API (SysON). Heuristic type/kind inference from PartDefinitions and Ports.

embgen import sysml --json-file model.json -o system.yml
embgen import sysml --base-url URL --project-id ID

One YAML, Four Languages

A single declarative system definition generates consistent code across all language boundaries.

system.yml (Input)

system:
  name: sensor_platform
  version: "1.0.0"

components:
  - id: adc_frontend
    type: fpga
    provides:
      - id: adc_ctrl
        kind: register
        fields:
          - name: enable
            bits: "0"
            access: rw
          - name: sample_rate
            bits: "15:8"
            access: rw
      - id: adc_data
        kind: stream
        data_type: int16

  - id: signal_proc
    type: cpp
    consumes: [adc_frontend.adc_ctrl,
                 adc_frontend.adc_data]

  - id: test_gui
    type: python
    consumes: [signal_proc.processed]

Generated Output

embgen generate system.yml --targets vhdl,c,cpp,python

gen/
  vhdl/
    adc_frontend_adc_ctrl_pkg.vhd
    adc_frontend_adc_ctrl_axi.vhd
    adc_frontend_adc_data_axis.vhd
  c/
    adc_frontend_adc_ctrl.h
    adc_frontend_adc_data_stream.h
  cpp/
    adc_frontend_adc_ctrl_wrapper.hpp
    adc_frontend_adc_data_buffer.hpp
  python/
    adc_frontend_adc_ctrl.py
  glue/
    fpga_to_c_adc_ctrl_hal.c
    fpga_to_c_adc_data_dma.c
    c_to_cpp_adc_ctrl_bridge.cpp
    cpp_to_python_pybind.cpp
  interfaces.yaml

15 file(s) generated (15 written, 0 unchanged)

License Model

Open-core: Free to start, professional features when you need them.

Community

Free

For evaluation and small projects

  • Register interface type
  • 1 target language (VHDL or C)
  • embgen validate + generate
  • embgen info + schema
  • No glue code
  • No import/export
Recommended

Professional

On Request

For productive embedded teams

  • All 5 interface types
  • All 4 targets (VHDL, C, C++, Python)
  • Automatic glue code
  • Manifest, Diagram, Diff, SBOM
  • Compliance reports
  • EA/XMI import, template overrides

Enterprise

On Request

For Large Enterprises and OEMs

  • Everything from Professional
  • SystemRDL Import
  • IP-XACT Import + Export (IEEE 1685)
  • SysML v2 Import (JSON + REST API)
  • Unlimited components
  • Priority support

embgen + embtrace

Two tools, one end-to-end workflow for CRA-compliant embedded systems.

Seamless Integration

  • embgen generates type-safe interfaces and produces interfaces.yaml as a manifest
  • embtrace uses interfaces.yaml as input for interface SBOM and compliance tracking
  • CycloneDX SBOM from embgen feeds directly into embtrace SBOM merge
  • Compliance reports from embgen become part of the embtrace evidence package

Architecture

              embgen                    embtrace
         ┌──────────────┐         ┌──────────────────┐
         │  system.yml  │         │  Yocto/Buildroot │
         └──────┬───────┘         └────────┬─────────┘
                │                          │
         embgen generate           embtrace sbom import
                │                          │
         ┌──────┴───────┐         ┌────────┴─────────┐
         │ VHDL, C, C++ │         │   Product SBOM   │
         │ Python, Glue │         │  (CycloneDX 1.5) │
         └──────┬───────┘         └────────┬─────────┘
                │                          │
         ┌──────┴───────┐                  │
         │ interfaces   │──────────────────►│
         │   .yaml      │  Interface-SBOM   │
         └──────────────┘                  │
                                           │
                                  ┌────────┴─────────┐
                                  │  CRA Evidence    │
                                  │  Package         │
                                  └──────────────────┘
Ostfildern near Stuttgart, Germany

Developed by Innomatica GmbH — based on over 10 years of experience in embedded software development for heterogeneous SoC platforms.

embgen was born from daily work with the TC4 test system — 23 Zynq modules with FPGA, Cortex-A53, Cortex-R5F and Python test environment. Real-world dogfooding instead of theoretical feature lists.

536 Tests 91% Coverage mypy --strict v1.0.0

Ready for Consistent Interfaces?

We help embedded teams automate their interface layers — from the YAML definition to the generated code.

[email protected]

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